1. Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for memory-mapped register caching.
2. Description of the Related Art
Current throughput processing implementations use highly threaded processor architectures to compensate for memory access and execution latencies. With this approach, each thread has its own set of registers within a dedicated Main Register File (MRF), yielding an enormous register file which consumes a significant amount of power.
In current implementations, the MRF is not directly related to the L1 data cache. Consequently, whenever there is a load operation, data must first be read from the memory subsystem (possibly from the cache) and placed into the MRF, consuming processing cycles and space within the MRF.